Design and implementation of a five-stage pipelined RISC processor with predicated instruction execution, described in Verilog. Developed as a team project.
Processor architecture
Datapath and control unit of a single-cycle processor, designed and verified in Logisim. Developed as a team project.
VLSI design
A 16-bit physical unclonable function array built from Schmitt-trigger-assisted SRAM cells. Covers schematic and layout design, transistor-level simulation and a readout testbench.
A baseline master-slave D flip-flop and a lower-power variant, integrated into a 4-bit register and counter, with a transistor-level comparison of the two designs. Developed as a team project.
Embedded and systems
An autonomous maze-solving robot built on an ESP32 and a flood-fill algorithm. Solving strategies were first evaluated in a Python simulator before moving to the hardware.
A reaction-time game for two players on a PIC16F877A microcontroller with LCD output, written in assembly and verified in Proteus simulation.
A traffic light controller for Linux, written in C, that coordinates multiple processes through message queues, shared memory, semaphores, pipes and signals.
Control systems
Simulation of a DC motor under P, PI and PID control, evaluated across several load torque conditions.
Services and collaboration
I am available for work in digital design and RTL, processor architecture, VLSI circuit design and simulation, and embedded firmware. For service inquiries or collaboration, please get in touch: